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SMB206A/7a/8 a preliminary 1 (see last page) summit microelectronics, inc. 2012 ? 757 n. mary ave ? sunnyvale ca 94085 ? phone 408 523 - 1000 ? fax 408 523 - 1266 http://www.summitmicro.com/ 2147 2.4 2/23/2012 1 dual programmable b uck regulators with integrated mosfets and digital control features ? dual step - down dc- dc outputs - integrated power mosfet switches - 1a -3 a output current with built in current limit - input voltage range: +4.5v to +16v - output voltage +0.8v to +5.0v (+/ - 2.5% accuracy) - automatic pfm mode for light load efficiency - integr ated frequency compensation ? integrated power control and programmability - i 2 c digital or pin control (enable) - static and dynamic programmable output voltage ? 128 levels of output voltage settings ? ?coarse? nominal setpoint ? 0.8v - 1.8v and 2.3/2.5/3.0/3.3/5.0v ? ?fine? margining ? +1.14% to +7.95% (vs. coarse setting) - pwm frequency 500- 1000khz with 180 o interleave - output enable and power up/down sequence - programmable output softstart/stop - output uv monitoring with pgood/reset output applications ? digital lcd/plasm a tv ? digital set - top box/pvr/dvr ? datacom/telecom equipment the smb206 a/7a/8a are highly integrated and flexible d ual - output dc - dc regulator s designed for use in a wide variety of applications. high i ntegration reduces system cost and component count , while the built - in non - volatile digital programmability cuts development t ime by allowing system designers to custom tailor the devic e to suit almost any application. the SMB206A/7a/8a include s integrated high - side mo sfet switches for up to 1a -3 a continuous output current. programmable output voltages as low as +0.8v support t he latest vlsi digital cores. minimum external components result in a very compact solution size for space constrained applications. s ophisticated power control/monitoring functions required by many systems are built - in and accessible via digital i 2 c in terface. these include digitally programmable output voltage setpoint, power - up/down softstart and sequencing, independent enable/disable, output uv monitoring with power good/reset out put. additionally , fine resolution voltage margining is provided to al low for sophisticated system optimization. the integration of features and built - in flexibility of the SMB206A/7a/8a allow the system designer to create a ?platform solution? that can be easily modified without hardware changes. the SMB206A/7a/8a are we ll suited to applications with an input range of +4.5 v to +16v. the operating temperature range is - 40 o c to +85 o c and the available packages are 3mm x 3mm 20 -pad qfn or 6.5mm x 6.4mm tssop -24. memory cpu/soc SMB206A/7a/8a step-down 1 int. fet system control and monitoring pgood/reset output enable inputs +4.5v to +16v dc in step-down 0 int. fet 0.8v-vin (prog.) up to 1a-3a 0.8v-vin (prog.) up to 1a-3a i2c i/f SMB206A - 3a+3a smb207a - 1a+1a smb208a - 2a+2a figure 1 - simplified application features & applications introduction
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 2 digital interface/non - volatile programming the built - in seri al digital i 2 c/smbus compatible port and built - in non - volatile programming bring several benefits to power supply design with the SMB206A/7a/8a . many external components are eliminated that would otherwise be used to set configuration and parametric values . additionally , the digital interface allows for quick and easy development and d ebug without hardware changes. finally, after the non - volatile power - up configuration , the serial port can be used to re - program the SMB206A/7a/8a by host softwar e after the system is running. for quick programming development and debug use summit?s prebuilt evaluation kit including a pc - based g raphical user interface (gui). dual pwm dc - dc regulators the SMB206A/7a/8a contain s two integrated pwm dc - dc step - down (buck) regulato r(s) with identical features and functions. the input voltage range is +4.5v to +16v to support a wide v ariety of system applications. the outputs support a full 1a - 3 a continuous output current with a built - in cycle - by - cycle current limit. the output volta ge range is +0.8v and +5.0v and fully programmable in non - volatile (static) or volatile (dynamic, on - the - fly ) via the serial digital interface. the nominal ?coarse? (100mv steps) voltage programming provides flexibility for various types of loads without h ardware changes. in the SMB206A/7a/8a the ?fine? programming provides ?margining? capability for sophisticated system validation and optimization . built - in high - side mosfets work in conjunction with external schottky diode rectifiers in constant frequency pwm - mode at high load currents or high efficiency pulse s kipping pfm - mode at light loads. switching frequency i s programmable (500khz/1000khz) to trade off efficiency and component size. each output switches 180 o out of phase with the other to reduce in put ripple current, switching noise and input capacitance requirement. bootstrapped high - side drive improves efficiency and extends the operating voltage range. frequency compensation is fully integrated to further reduce component count and cost. power control/management functions the SMB206A/7a/8a integrate s several power management functions that are typically otherwise p erformed by external circuits. these include output sequencing with programmable timing, ha rdware or software - based output enable/dis able, and programmable softstart timing. also , the output voltages are monitored with a programmable pgood/reset output (pgood asserts imm ediately, reset delays 125ms). software enable bits and hardware enable pins work together to provide flexible power u p/down and manual/auto sequencing . the SMB206A/7a/8a also support s digitally progra mmable dynamic output voltage. the non - volatile setting determines the power - up/static value but it can be re - programmed by softwar e via the serial interface. the s ettings are +0.8v to +5.0v and can support dynamic voltage/clock cpu cores or low power memory modes. general description
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 3 smb20 6a /7a/8a gnd pvin(4) en0 pgood/reset +4.5v to +16v vdd 4.7uf +0.8v to vin @ 1a-3a 1uf 2.2uh-6.8uh sw0(2) 4.7/10/ 22uf fb0 en1 +0.8v to vin @ 1a-3a 2.2uh-6.8uh sw1(2) 4.7/10/ 22uf fb1 scl sda 0.1uf bst0 0.1uf bst1 internal 5v ldo uvlo pwm pwm i2c i/f digital control nv otp oscillator 0 1 output voltage sequencer softstart vref 1a-3a 1a-3a avin SMB206A - 3a+3a smb207a - 1a+1a smb208a - 2a+2a optional for custom output voltages optional for custom output voltages *contact factory for tssop package qfn - 20 pin # tssop pin #* pin name pin type pin description 16, 17, 19, 20 3, 4, 22, 23 pvin power power input - connect to +4.5v to +16v source. bypass with 4.7uf mlcc 18 2 avin power analog p ower input - connect to +4.5v to +16v source (same as pvin) 12 18 vdd power internal vdd - +5v internal supply. bypass with 1uf typical mlcc 4, pad 8, pad gnd ground ground ? connect to pcb isolated ground 9 15 scl input i 2 c clock 10 16 sda i/o i 2 c data 7,6 11, 10 en(0/1) input enable 0/1 ? enables output, high true 14, 15, 1, 2 20, 21, 5, 6 sw0/1 output switch node 0/1 ? connect to output inductors 13, 3 19, 7 bst0/1 input bootstrap input ? connect to 0.1uf capacitor to switch node 11, 5 17, 9 fb0/1 input feedback input 0/1 ? connect to output sense node 8 14 pgood/ reset output powergood/reset output ? output uv monitor signal (high true, open drain) na 1, 12, 13, 24 nc nc not connected pin description figure 2 - typical application
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 4 1 smb20 6a /7a/8a 3mm x 3mm qfn-20 (top view) pad = gnd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 sw1 sw1 bst1 gnd fb1 en1 en0 pgood/ reset scl sda sw0 sw0 bst0 vdd fb0 pvin1 pvin1 pvin0 pvin0 avin 1 smb20 6a /7a/8a 6.4mm x 6.5mm tssop-24 (exposed pad) (top view) pad = gnd 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 sw1 sw1 bst1 gnd fb1 en1 en0 pgood/reset scl sda sw0 sw0 bst0 vdd fb0 pvin1 pvin1 pvin0 pvin0 avin 24 23 22 21 nc nc nc nc *contact factory for tssop package figure 3 - package and pinout
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 5 dont care vout0 vout1 vout0 vout1 pgood 0.5/1/4/8ms 0.5/1/4/8ms reset 125ms pvin v uvlo v pg1 (90% vout1) 1ms vdd v pg0 (90% vout0) en0,1 10ms auto sequence bits = 01b 1-50ms static and dynamic output voltage settings 128 -levels 0.8v-1.8v 100mv steps plus 2.3/2.5/3.0/3.3/5.0v figure 4 - typical output timing diagram figure 5 - typical output sequence diagram vout0 0.5/1ms 0.5/1/4/8ms 1ms vout1 autosequence = 11b vout0 v pg1 v pg0 vout1 autosequence = 01b vout0 autosequence = 10b en0/1 vout1 v pg1 v pg0 v pg1 v pg0 note: sequence delay = 0ms, [03h] = 00
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 6 output states en0 pin en1 pin ch0 enable bit ch1 enable bit chip state output b ehavior ch0 ch1 low low x x shutdown disabled disabled low high x 0 shutdown disabled disabled high low 0 x standby disabled disabled low high x 1 shutdo wn disabled enabled high low 1 x active enabled disabled high high 0 0 standby disabled disabled high high 0 1 active disabled enabled high high 1 0 active enabled disabled high high 1 1 active enabled enabled note : ?x? denotes a ?don?t care? state o utput sequencing auto sequence [02h bits3:2] output b ehavior* 0 0 ch0/ch1 respond independently to enable pins/bits, no auto - sequence 0 1 ch1 is dependent on ch0 state. ch1 always turns on after and turns off before ch0 (based on pgood signals)** 1 0 ch0 is dependent on ch1 state. ch0 always turns on after and turns off before ch1 (based on pgood signals)** 1 1 ch0 and ch1 turn on and off together** *power down timing is not specifically controlled and is dependent on load current and output capacit ance - slew rate is not guaranteed. assumes input uvlo is cleared. if auto - sequence bit are other than 00b then fault conditions (oc, ot etc.) may shutdown both outputs. **assumes en pins and enable bits are in the intended states per the output state t able. pgood/reset assignment [02h bits7:6] vout0 vout1 pgood/reset output 00 vout0 < v pg0 vout1 < v pg1 low vout0 < v pg0 vout1 > v pg1 low vout0 > v pg0 vout1 < v pg1 low vout0 > v pg0 vout1 > v pg1 high 01 don?t care vout1 < v pg1 low don?t care vo ut1 > v pg1 high 10 vout0 < v pg0 don?t care low vout0 > v pg0 don?t care high 11 don?t care don?t care high output state/sequence logic tables powergood/reset output logic table
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 7 iout > imax? (continuously monitored) yes terminate current pwm cycle vout < vuv? pwm stop 10ms timeout no yes no softstart softstart complete? yes no iout > imax? (continuously monitored) no yes skip 7 pwm cycles steady state operation figure 6 - overcurrent behavior (per output)
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 8 absolute maximum ratings recommended operating conditions storage temperature ........................... - 65 c to +150c junction temperature .......................... - 55 c to +150c lead solder temperature (10s) ........................... 300 c terminal voltage with respect to gnd: pvin, avin, sw, en0/1 ................................ +18v bst, pvin ..................................................... +6.5v all others ...................................................... +6.5v output short circuit current (any single pin) ............ 3a esd rating per jedec (hbm) vdd .............................................................. 1000 v all other pins ............................................... 2000 v latch - up testing per jedec ............................. 100ma note - the device is not guaranteed to function outside its operating rating. stresses listed under absolute maximum rat ings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. exposure to any abs olute maximum rating for extended periods may affect device performance and reliability. devices are esd sensitive. handling precautions are recommended. ambient temperature range ................ - 4 0c to +85c junction temperature range ............. - 4 0c to +125 c pvin, avin .............................................. +4.5 v to +16v package thermal resistance ( ja ) 20 pad 3mm x 3mm qfn .................................. 47 o c/w 24 pin 6.5mm x 6.4mm tssop * ........................ 38 o c/w moisture classification ................................................... .................................... level 3 (msl 3) per j - std - 020 reliability characteristics data retention ................................................. 20 years *contact factory for tssop package pvin = +12v, vdd = +5v, t a = t j = - 4 0c to +85c unless otherwise noted. typical values are +25 c, note 1 ,2 symbol parameter conditions min typ max unit main supply v in main input supply voltage (pvin) 4.5 16 v v dd internal ldo supply voltage (vdd) v in >5.5v, i dd <10ma 4.5 5.5 v i in input supply current (pvin) outputs enabled, no load 2 10 ma i in - stby standby supply current en pins high, output enable bits disabled, i 2 c active 0.3 1 ma i in - shdn shutdown supply current en pins low 1 5 ua v uvlo input undervoltage lockout (vdd monitored) vdd rising 3.75 4.0 4.25 v vdd falling (relative to vdd rising) - 10 % t shdn thermal shutdown threshold temp rising 140 150 o c t hyst thermal shutdown hysteresis 20 o c note 1: parametric t olerances are only guaranteed for factory - programmed settings. changing configuration settings from that reflected in the customer specific csir code may result in inaccuracies exceeding those specified above. note 2: min/max limits are guaranteed by test, characterization or design . electrical operating characteristics
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 9 pvin = +12v, vdd = +5v, t a = t j = - 40c to +85c unless otherwise noted. typical values are at +25c, note 1 ,2 symbol parameter conditions min typ max unit step - down regulators (ch0,1) v out coarse output voltage progr ammable 0.8v - 1.8v (100mv steps) and 2. 3/2.5 /3.0/3.3/5.0v 0.1a to full dc load - 2.5 +2.5 % dv outf fine output voltage offse t programmable +1.14% to 7.95% relative to coarse output voltage (3 - bits) 0 +7.95 % srv out dynamic output voltage slew rate (note 3) v fb slew from completion of i 2 c write (0.8v - 1.8v only) 103 128 153 us/step ?v line line regulation ?v out / ? v in (10v < v in < 14v) 1 3 mv/v i fb feedback pin current 1 ua f sw pwm switching frequency programmable 500/1000khz - 15 15 % phase interleave ch0 vs. ch1 180 deg r dsh high side fet switch resistance SMB206A/7a/8a 250 400 m ? r dsl low side fet switch resistance 10 ? i lim switch peak current limit smb207a (ch0/ch1) 1.5/1.5 2/2 a smb208 a (ch0/ch1) 3/3 4/4 a smb206 a (ch0/ch1) 4.5/4.5 6/6 a t ho startup holdoff time 10 ms t ss softstart/stop slew program mable 0.5/1.0ms (1 bit) - 20 +20 % t seq sequence delay programmable 1.5 - 50ms (2 bits) - 20 +20 % v pg0,1 output pgood/reset threshold v out0,1 rising relative to nominal coarse setting 85 90 95 % t bpg pgood/reset blanking time after last step of v fb durin g dynamic output voltage (note 3) 192 us t uvpg output pgood/reset glitch filter v out falling 32 us t rst reset output delay v out rising 100 125 200 ms v uv output undervoltage threshold (short circuit) % of v out , v out falling 52.5 62.5 72.5 % v hyst -uv uv threshold hysteresis (short circuit) % of v out , v out rising 3 % logic inputs/outputs (en0/1, sda/scl, pgood/reset) v ih input high voltage 1.4 v v il input low 0.6 v v ol open drain outputs i sink = 3ma 0.3 v note 1: parametric toleranc es are only guaranteed for factory - programmed settings. changing configuration settings from that reflected in the customer specific csir code may result in inaccuracies exceeding those specified above. note 2: min/max limits guaranteed by test, characteri zation or design . note 3: ?coarse? volatile output voltage writes above 1.8v setting requires a channel disable/re - enable to take effect . electrical operating characteristics (continued)
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 10 pvin = +12v, vdd = +5v, t a = 0c to +85c unless otherwise noted. typical values are +25c, note 1 ,2 symbol pa rameter conditions 400khz min typ max units f scl scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 0.6 s t buf bus free time between a stop and a start condition before new transmission - note 1 1.3 s t s u:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:sto stop condition setup time 0.6 s t r scl and sda rise time 20 + 0.1c b 300 ns t f scl and sda fall time 20 + 0.1c b 300 ns t su:dat data in setup time 100 ns t hd:dat data in hold time 0 0.9 s t n noise filter scl and sda noise suppression 100 ns note 1: parametric tolerances are only guaranteed for factory - programmed settings. changing configuration settings from that reflected in the customer spe cific csir code may result in inaccuracies exceeding those specified above. note 2: min/max limits guaranteed by test, characterization or design . t r t f t high t low t su:sta t hd:sta t su:dat t hd:dat t su:sto t buf t dh t aa scl sda (in) sda (out) t w r (for w rite operation only) i 2 c/smbus serial interfa ce electrical specifications figure 7 - i 2 c/smbus timing diagram
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 11 typical performance graphs typical performance graphs 20.0% 25.0% 30.0% 35.0% 40.0% 45.0% 50.0% 55.0% 60.0% 65.0% 70.0% 75.0% 80.0% 85.0% 90.0% 0.01 0.10 efficiency(%) load(a) efficiency vout 5.0v vout 3.30v vout 2.50v vout 1.80v vout 1.50v vout 1.20v vout 1.0v vout 0.8v conditions: vin = 12v, vout = 0 .8v, 1v, 1.2v, 1.5v, 1.8v, 2.5v, 3.3v, 5.0v, freq = 500khz figure 10: smb208a light load efficiency g raph 60.0% 62.0% 64.0% 66.0% 68.0% 70.0% 72.0% 74.0% 76.0% 78.0% 80.0% 82.0% 84.0% 86.0% 88.0% 90.0% 92.0% 94.0% 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 efficiency(%) load(a) efficiency vout 5.0v vout 3.30v vout 2.50v vout 1.80v vout 1.50v vout 1.20v vout 1.0v vout 0.8v conditions: vin = 12v, vout = 0.8v, 1v, 1. 2v, 1.5v, 1.8v, 2.5v, 3.3v, 5.0v, freq = 500khz figure 11 : smb208a full l oa d efficiency graph 25.0% 30.0% 35.0% 40.0% 45.0% 50.0% 55.0% 60.0% 65.0% 70.0% 75.0% 80.0% 85.0% 90.0% 0.01 0.10 efficiency(%) load(a) efficiency vout 5.0v vout 3.30v vout 2.50v vout 1.80v vout 1.50v vout 1.20v vout 1.0v vout 0.8v conditions: vin = 12v, vout = 0.8v, 1v, 1.2v, 1.5v, 1.8v, 2.5v, 3.3v, 5.0v, freq = 500khz figure 8 : SMB206A light load ef ficiency graph 60.0% 62.0% 64.0% 66.0% 68.0% 70.0% 72.0% 74.0% 76.0% 78.0% 80.0% 82.0% 84.0% 86.0% 88.0% 90.0% 92.0% 94.0% 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 efficiency(%) load(a) efficiency vout 5.0v vout 3.30v vout 2.50v vout 1.80v vout 1.50v vout 1.20v vout 1.0v vout 0.8v conditions: vin = 12v, vout = 0. 8v, 1v, 1.2v, 1.5v, 1.8v, 2.5v, 3.3v, 5.0v, freq = 500khz figure 9: SMB206A full l oad efficiency graph
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 12 typical performance graphs (continued) typical performance graphs (continued) typical performance graphs (continued) figure 1 2 : bode plot of smb208a circuit displayed in figure 20 with full load
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 13 00h ? i 2 c slave address (nv, r/w) ? factory programmable only bit7 bit6 bit5 bit4 bit 3 bit2 bit1 bit0 i 2 c slave address (read only) 0 0 0 0 0 0 0 x lsb for r/w in i 2 c format bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 volatile writes to 01h/02h* x x x x x x x 0 0 = enable volatile writes to vout 1 = disable volatile writes to vout 01h/02h ? channel 0/1 output voltage (nv, r/w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 coarse/nominal output voltage (v) 0 0 0 0 x x x x 0.800 0 0 0 1 x x x x 0.900 . . 1 0 0 1 x x x x 1.700 1 0 1 0 x x x x 1.800 1 0 1 1 x x x x 2.300 1 1 0 0 x x x x 2.500 1 1 0 1 x x x x 3.000 1 1 1 0 x x x x 3.300 1 1 1 1 x x x x 5.000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 fine output vol tage offset % x x x x 0 0 0 x 0 x x x x 0 0 1 x +1.14 x x x x 0 1 0 x +2.27 x x x x 0 1 1 x +3.41 x x x x 1 0 0 x +4 .55 x x x x 1 0 1 x +5.68 x x x x 1 1 0 x +6.82 x x x x 1 1 1 x +7.95 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved x x x x x x x 0 unused *?coarse? volatile output voltage writes above 1.8v setting requires a channel disable/re - enable to take ef fect configuration registers
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 14 03h ? output sequencing/softstart (nv, r/w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pgood/reset assignment 0 0 x x x x x x 00 = both outputs (dual output only) 01 = ch1 only (dual output only) 10 = ch0 only 11 = none (ignore) bit7 bit6 bit5 bi t4 bit3 bit2 bit1 bit0 pgood/reset x x 0 x x x x x 0 = pgood 1 = reset bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 output softstart (ms) x x x 0 x x x x see below bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 automatic output power - up sequence (dual output only) x x x x 0 0 x x 00 = disabled (pin/bit control) 01 = ch0 then ch1 10 = ch1 then ch0 11 = ch1 and ch0 start together bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ch1 output enable (dual output only) x x x x x x 0 x 0 = disable 1 = enable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ch0 output enable x x x x x x x 0 0 = disable 1 = enable 04h ? output sequencing/softstart (nv, r/w) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved 0 0 0 0 0 x x x unused bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 output softstart (ms) x x x 0 x x x x see below bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 pwm frequency (khz) x x x x x 0 x x 0 = 500 1= 1000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sequence delay (ms) (dual output only) x x x x x x 0 0 00 = 1.5 01 = 12.5 10 = 25 11 = 50 03h[4] 04h[3] output softstart time (ms) 0 0 1 0 1 8 1 0 0.5 1 1 4 configuration registers (continued)
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 15 applications information device operation power supply (pvin, avin, vdd, gnd) the SMB206A/7a/8a can be powered from an input voltage of between 4.5 v - 16 v applied to the pvin pins, avin and ground. a n internal ldo (vdd) is used to supply 5.0v for the gate drive of the internal n - channel mosfet . once the voltage applied to pvin is above 4.0v (uvlo) and an enx pin is taken high, the channel assigned to the enx p in will begin switching provided the smb2 06a/7a/8a is programmed for pin control (see ?power - on/off control? sections). please note that the en pin(s) serve dual functions both enabling/disabling channels and serving to place the SMB206A/7a/8a in shutdown or standby modes. power - on/off control (e n0, en1, i 2 c control) the output(s) on the SMB206A/7a/8a can be turned on/off in a number of different ways: the enx pins can be pulled high (to vin ) and once power is applied, the channels will turn on according to one of the following user assigned (prog rammed) sequences: 1. channels turn on according to enx pin(s) 2. channel 0 followed by channel 1 3. channel 1 followed by channel 0 4. channel 0 and channel 1 start together the SMB206A/7a/8a also employs i 2 c control of the outputs, requiring only that the enx pins be pulled high in order to facilitate this control. using i 2 c control allows all the above sequence combinations. finally, taking en0 low places the pa rt in low current shutdown mode (see ?output state/sequence logic tables? section). swx pin(s) the int ernal n - channel mosfet(s)? source connection appears at the sw nodes where the external inductor, bootstrap capacitor , and schottky diode are all connected. the internal mosfet gate is driven by the vdd supply working in conjunction with the bootstrap capa citor to allow the mosfet gate to be driven to vin plus 5v . the mosfet current is internally limited and the switching cycle is terminated when the current limit threshold is exceeded. an internal low current, low - side, n - channel mosfet is provided for kee ping the bootstrap capaci tor charged when there is no or minimal load on the output. this mosfet is not to be used in place of the external schottky as it will not support high currents. connections to the inductor, schottky , and bootstrap capacitor must b e as short as possible and the trace width maximized to the inductor and schottky paths. minimum trace w idth should be at least 0.050?. fb each channel has a unique fb (feedback) pin where the output voltage is internally connected to the inverting input o f the internal transconductance amplifier. the SMB206A/7a/8a requires no external resistive divider from the output to the fb node for output voltages between 0.8v to 5.0v. further, the SMB206A/7a/8a requires no external compensation components as the comp ensation is optimized internal to the part. pgood/reset this open drain pin indicates that all channels assigned to this pin are functional and within the user - programmed values plus or minus the amount for under and overvoltage. each output can have a pgo od/reset associated with it or one can choose not to have this function associated with one or all channels. the reset pin is low when the channel is off , or out of spec for voltage , or an overcurrent and will go high when the channels(s) are within spec a fter a delay of 125ms. the pgood function acts as the reset with the exception that is has no delay once all channels are within spec (see ? powergood/reset output logic table ? section). bootstrap this pin connects to a high quality, low - esr ceramic capacit or of 0.1uf to power the internal gate drive to vin plus vdd (5 .0 v nominal). the bst capacitor is initially charged to 5 .0 v when the part is turned on and the output is off. when the output is turned on, the capacitor voltage is refreshed each time the int ernal mosfet is turned off via the external schottky when it is forward biased. when there is little or no load, the SMB206A/7a/8a refreshes the bootstrap capacitor as required. overtemperature the SMB206A/7a/8a family contains an overtemperature shutdown circuit that shuts down all channels when the die temperature exceeds 140 c (nominal). operation may resume when the internal die temperature falls to below 120 c (nominal).
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 16 applications information programmable device parameters output voltage(s) output voltages for all channel s are user programmable from 0.8v to 5.0v according to the below: 0.8v to 1.8v in 0.1v increments followed by; 2.3v, 2.5v, 3.0v, 3.3v, 5.0v for any setting, a fine adjust is available whereby the user can fine tune the output voltage in steps of +1.14% of nominal up to +7.95% of nominal. operating frequency selection the SMB206A/7a/8a switch frequency is user programmable to operate at 500khz or 1mhz. this setting must not be changed when the outputs are enabled. first, disable the output and then select th e frequency. soft start two soft start ramp times are avail able, a ffecting both channels. with a selection of 0.5ms or 1.0ms, choose the value that best suits the application keeping in mind that these softstart periods apply to the programmed output volta ge and will cause higher turn - on slew rates when higher output voltages are programmed. note: when using large values of output capacitance use the below formula to ensure the output can start within the programmed soft start interval: ? ??? ? ? ? ?? ????????? ( ? ) + ? ??? ? ??? where: c out = total output capacitance in farads v out = nominal output voltage setting i out = maximum output load current (during the ss interval) softsstart = softstart time in seconds i lim = 3a usi ng too large of output capacitance combined with the output load can lead to a failed softstart event which will force the part to rest for 10ms and retry (see figure 6). power - on sequencing slots power on sequencing with multiple channels is user programmable as shown below: 1. ch 0 > ch 1 2. ch 1 > ch 0 3. ch 0 & ch 1 turn on are coincident 4. disabled. this mean the channels will not turn on until the associated en pin is pulled high. power - on sequencing delay(s) four sequence on time delays are available: 1. 5ms, 12.5ms, 25ms, and 50ms . this is the delay time between the first channel reaching 90% of nominal to the time the second channel begins turning on ( figure 13 ). this same delay time applies to turn off but the channel sequence position is reversed ( fi gure 1 4 ). cascaded sequencing as shown in figure 1 3 , the SMB206A/7a/8a family of controllers features cascaded channel sequencing whereby a channel (in a dual - channel device) will turn on once the first channel has reached its uv threshold and the ?power o n sequencing delay? period is expired. note that in figure 1 4 , the channels sequence off in the opposite order. cascaded sequencing requires the controller be programmed for the channels to come on at different times. cascaded sequencing between devices is also possible by connecting the pgood pin of the first controller to the enable of the second or subsequent controller. this allows cascaded sequencing for power - on but does not permit power off sequencing.
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 17 applications information figure 13 : ch 0 to ch 1 sequence on with 1.5ms delay figure 14 : ch 1 to ch 0 sequence off with 1.5ms delay
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 18 applications information smb20 6a /7a/8a gnd pvin(4) en0 pgood/reset +4.5v to +16v vdd 4.7uf +0.8v to vin @ 1a-3a 1uf 2.2uh-6.8uh sw0(2) 4.7/10/ 22uf fb0 en1 +0.8v to vin @ 1a-3a 2.2uh-6.8uh sw1(2) 4.7/10/ 22uf fb1 scl sda 0.1uf bst0 0.1uf bst1 internal 5v ldo uvlo pwm pwm i2c i/f digital control nv otp oscillator 0 1 output voltage sequencer softstart vref 1a-3a 1a-3a avin cascaded auto sequencing options: 1.) 0,1,2,3 2.) 0,1,3,2 3.) 1,0,2,3 4.) 1,0,3,2 optional for custom output voltages optional for custom output voltages smb20 6a /7a/8a gnd pvin(4) en0 pgood/reset +4.5v to +16v vdd 4.7uf +0.8v to vin @ 1a-3a 1uf 2.2uh-6.8uh sw0(2) 4.7/10/ 22uf fb0 en1 +0.8v to vin @ 1a-3a 2.2uh-6.8uh sw1(2) 4.7/10/ 22uf fb1 scl sda 0.1uf bst0 0.1uf bst1 internal 5v ldo uvlo pwm pwm i2c i/f digital control nv otp oscillator 0 1 output voltage sequencer softstart vref 1a-3a 1a-3a avin optional for custom output voltages optional for custom output voltages output 0 output 1 output 2 output 3 figure 15 : cascaded auto sequencing
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 19 applications information external component se lection output l & c the inductor and filter capacitor is chosen according to system requirements. these include the minimum to maximum input voltage, nominal output voltage, maximum output current and maximum allowable output rip ple. for these criteria we use e quations 1 - 3 to determine the optimal value of l and c. the chosen output capacitor?s esr will impact the system ripple and therefore must be taken into account. for this, we use equation 3 to determine the maximum allowable esr. eq 1. ( ) out sw out i f v l 4 . 0 1 ? where is the duty cycle in out v v eq 2. ) ( p p l p p c i v esr out ? ? eq 3. p p sw p lp v f i c ? ? 8 a practical example involves the below system requirements: v in = 12v v out = 1.8v i out(max) = 2.0a (smb208 a ), use 50% of this amount t o guarantee the inductor current is in ccm for most loads. p - p ripple (max) = 50mv first, solve for the minimum inductor value: 6.8uh use : 10 4 . 7 0 . 1 10 5 4 . 0 12 8 . 1 1 8 . 1 6 5 ? ? ? ? ? ? ? ? ? ? ? ? ? l now find the inductor ripple current: ( ) a f l v i sw out p lp 45 . 0 10 5 10 8 . 6 85 . 0 8 . 1 1 5 5 = ? ? ? ? = ? ? = ? next , solve for the maximu m allowable esr for the output capacitor , followed by the minimum capacitor value required to meet the output ripple spec given the ripple current flowing through the inductor. ? m esr out c 24 1 . 2 05 . 0 6 5 10 25 . 2 05 . 0 10 5 8 45 . 0 ? ? ? ? ? c the calculated value of capac itance is much less than the minimum recommended for sta ble loop operation of the smb208 a (10 uf), so choose 2 x 10 uf capacitors with each hav ing a maximum esr at 500khz of 24milliohms (0.024/2 = 0.012 ) or less.
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 20 applications information figure 16 : transient load response: 5vin, 1.5vout 0.2a - 2a current step figure 17 : trans ient load response: 12 vin, 1.5vout 0.2a - 2a current step
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 21 applications information figure 18 : s mb207a detailed schematic smb207a bill of materials item# quantity description ref des manufacturer manufacturer p/n 1 1 10uf 25v ceramic x5r 1206 c1 panasonic ecj - 3yb1e106k 2 1 cap cer 4.7uf 6.3v x5r 0402 c3 panasonic ecj - 0eb0j475m 3 2 0.1uf 16v 10% x 7r 0402 c4, c8 epcos inc b37921c9104k60 4 2 cap cer 22uf 10v x5r 0805 c5, c9 panasonic ecj - 2fb1a226m 5 2 schottky diode, 3 pin, common anode d1, d2 diode inc sbr1u40lp - 7 6 2 4.7uh inductor 1.3a 20% 1210 smd l1, l2 taiyo yuden brl3225t4r7m 7 2 res 681k ohm 1/16w 1% 0402 r1, r2 any 8 1 res 47k ohm 1/16w 5% 0402 r3 any 9 1 dc- dc controller u1 summit micro smb207a
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 22 applications information top layer bottom layer figure 19 : typical smb207a layout displaying placement of critical components and trace routing
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 23 applications information f i gure 20 : smb208a detailed schematic smb208a bill of materials item number qty description ref des manufacturer manufacturer p/n 1 1 10uf 25v ceramic x5r 1206 c1 panasonic ecj - 3yb1e106k 2 1 cap cer 4.7uf 6.3v x5r 0402 c3 panasonic ecj - 0eb0j475m 3 2 0.1 uf 16v 10% x7r 0402 c4 c8 epcos inc b37921c9104k60 4 2 cap cer 22uf 10v x5r 0805 c5 c9 panasonic ecj - 2fb1a226m 5 2 schottky diode, 3 pin, common anode d1, d2 diode inc sbr1u40lp - 7 6 2 4.7uh inductor 1.3a 20% 1210 l1, l2 taiyo yuden brl3225t4r7m 7 2 res 681k ohm 1/16w 1% 0402 r1, r2 any 8 1 res 47k ohm 1/16w 5% 0402 r3 any 11 1 dc- dc controller u1 summit micro smb208a
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 24 applications information top layer bottom layer inner layer 1 inner layer 2 figure 21 : smb208a typical bottom layer layout display ing placement of critical components and trace routing
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 25 package dimensions (qfn - 20)
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 26 2xxy zzzz pin 1 summit part number xx = 05,06,07,08 y = "a" or non-"a" lot/date tracking code (summit use) drawing not to scale package dimensions (tssop - 24) *contact factory for tssop pack age
SMB206A/7a/8a preliminary summit microelectronics, inc. 2147 2.4 2/23/2012 27 smb2xxy z package n=20 pad qfn t =24 pin tssop summit part number xx = 05,06,07,08 y = "a" nnnn part number suffix specific requirements are contained in the suffix t l t = tape & reel environmental attribute l = 100% sn free, rohs compliant 2xxy zzzz pin 1 summit part number xx = 05,06,07,08 y = "a" lot/date tracking code (summit use) drawing not to scale notice note 1 - this is an preliminary data sheet that describes a summit product currently in development. it is meant sol ely as a product description and should not be used as a design tool. summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectro nics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein refl ect representative operating parameters, and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either sys tem or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been m inimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. revision 2.4 - this document supersedes all previous versions. please check the summit microelectr onics inc. web site at www.summitmicro.com for data sheet updates. ? copyright 2012 summit microelectronics, inc . programmable power for a green planet ? i 2 c is a trademark of philips corporation part marking ordering information *contact factory for tssop package

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